Vlsi Implementation Of Ternary Adder And Multiplier Using Tanner Tool

Abstract

In CMOS logic, only binary logic is taken into consideration for implementation. Binary connection increases in size on the VLSI chip with circuit complexity, degrading performance. The proposed answer to this problem is in MVL (Multi valued logic).The optimal radix for many MVL systems is ternary logic, which is often referred to as three-valued logic.The layout is made with the use of VLSI CMOS technology, and the proposed ADDER AND MULTIPLIER is developed and simulated using the Microwind EDA tool.