A Novel Realization of Multiplier Design for Signal Processing

Abstract

The multiplication operation is a need for all DigitalSignal Processing (DSP) applications. It includes addition and shift operations. Many
people have developed a wide range of concepts for computation systems with different design objectives in terms of power, area, and speed.
Digital signal processor (DSP), Fast Fourier Transform (FFT), and Multiply and Accumulate Unit are examples of applications based on its
regular structure (MAC). This research recommends two solutions, specifically for DSP systems, to boost speed and cut power usage. Four
2x2 LUT multipliers are utilized in proposed -1 Multiplier to show it on a 4x4 multiplier. The two multipliers that are being suggested are
designed with XILINX VIVADO software and are written in Verilog HDL. Additionally, the suggested multiplier’s latency, area, and power
usage are compared to those of traditional multipliers. Additionally, the simulation findings suggest that the work utilizes less power than
standard approaches, achieving only 3.751W in proposed-1 and 2.824W in proposed-2 as opposed to the traditional multiplier 4.804W, and
has demonstrated less latency.