Design And Implementaion Of Risc-V Quad Core Processor Architecture With Low Overhead For Fault Tolerant Applications
Electronic equipment become faster, more powerful, and more compact as technology advances. Nevertheless, system reliability suffers as a result of technology scaling. However, several device transistors are used for improving the scaling. Along with this issue, power dissipation is the other factor leading to the degradation of performance. In order to overcome the above said limitations, RISC – V architectures are preferred. RISC V architecture offers significant improvement in modularity, efficiency, performance, and ease of expansion. In a single chip Quad core processor there are four processing cores are mounted. Existing work uses dual-core CPUs, but instead of having two simultaneous instruction processors, it has four independent processors.In this work, a new quad-core processor architecture is proposed for improving the performance and detecting fault-tolerant applications. . The suggested processor uses low overhead to produce fault-tolerant outputs because of its reconfigurable feature, and it is implemented using Verilog HDL. The additional work of the proposed architecture is that the feature reduces the resource overhead and makes the processor energy-efficient by using all four processor cores to provide fault-tolerant results. The work is further synthesized using 180 nm CMOS process technology node and the resource utilization results are computed using cadence tool. The outcomes will be tested with current fault-tolerant CPUs.